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POWER10

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Last Updated: 18 January 2022

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General | Latest Info

POWER10

Launched2020
Designed byIBM , OpenPower partners
Common manufacturer(s)Samsung
Performance
Max. CPU clock rate+3.5 GHz to +4 GHz
Cache
L1 cache48+32 KB per core
L2 cache2 MB per core
L3 cache120 MB per chip
Architecture and classification
Min. feature size7 nm
MicroarchitectureP10
Instruction setPower ISA ( Power ISA v.3.1 )
Physical specifications
Cores15 SMT8 cores 30 SMT4 cores
Package(s)OLGA SCM and DCM
Socket(s)1-16
History
PredecessorPOWER9
SuccessorPOWER11

Ibm has revealed its 7 - nanometer POWER10 processor for Hybrid Cloud workloads, bringing feature that its lead architect is calling holy grail of industry: ability to pool petabytes of Memory between multiple servers, potentially enabling significant cost savings for data centers. Armonk, NY - base Big Blue say server processor, announced Monday, provides up to three times greater efficiency, workload capacity and container density than POWER9. Beyond its new Memory Inception feature for multi - petabyte memory clusters, upcoming chip also comes with memory encryption and artificial intelligence capabilities. Power10 - base servers are expected to become available in second half of 2021, IBM say. That would put IBM ahead of Intel in releasing 7nm server processor, though Intel has previously said its 10nm process is similar to 7nm nodes used by IBM and AMD, and its first 10nm server processors are set to begin shipping by end of this year. Amd, on other hand, has had 7nm server processors on market for roughly year. Ibm says its Memory Inception feature allows multiple POWER10 - base Systems to share multiple of Memory, which can improve Cloud capacity and economics for Memory - intensive applications from vendors like SAP and SAS Institute, as well as inferencing for large - Scale AI models. Bill Starke, distinguish engineer and POWER10 processor architect, says Memory Inception essentially allows POWER10 processor to trick system into thinking that memory in another system belongs to this system, and IT has significantly lower latency than traditional methods like remote direct Memory access over Mellanox InfiniBand interconnects. This is extremely low - latency way to basically use just speed of electricity through cable and nothing more in your way to get to other systems memories, he say. And what this really means is that this has kind of been holy grail of industry. Starke says Memory Inception has major implications for server costs, particularly because ability to pool memory among several systems means each rack does need to be overloaded with memory. Benefit Of This Is Kind Of Two - Fold, Especially In Cloud Settings Where Youre At Massive Scale, He Say. Instead of having to put lot of memory into every box so that I can make sure I can meet peak demands of that box, I could actually plug in more reasonable amount of memory in each box, saving lots and lots of infrastructure costs. And then, in case where I spike demand for memory, I can borrow that memory from my neighbors. Memory Inception can also enable new kinds of workloads that require massive amounts of memory normally would fit into one server box, according to Starke. What if I want computer to talk to petabyte of memory? Well, nobody how to build that today, he say.

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions.

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions

Design

Chips have completely reworked memory and I / O architecture Open Memory Interface Enables Extremely Low Latency And High Bandwidth RAM. Using serial memory communications to off chip controllers reduces signaling lanes to and from chip, increases bandwidth and makes processor agnostic towards what technology is in memory end, making system flexible and future proofed. Ram can be anything from DDR3 through DDR5 to GDDR and or Persistent storage Memory, all depending on what's practical for application. Ddr4 - Support for Up to 4 TB RAM, 410 GB / s, 10 ns latency GDDR6 - Up to GB / s Persistent storage - Up to 2 PB POWER10 enables encrypting of data with no performance penalty at every stage from RAM, across accelerators and cluster nodes to data at rest. Power10 comes with PowerAXON facility enabling chip to chip, system to system and OpenCAPI bus for accelerators, I / O and other high cache coherent peripherals. It manages communications between nodes in 16x socket SCM cluster or 4x socket DCM cluster. It also manages Memory semantics for clustering of systems, enabling load / store access from core up to 2 PB of RAM on entire POWER10 cluster. Ibm calls this Memory Inception. Both OMI and PowerAXON can handle 1 TB s communications off chip. Also in POWER10 PCIe 5. Scm has 32x DCM has 64x PCIe 5 lanes. Ibm and Nvidia agree that including NVLink in POWER10 would be somewhat redundant since PCIe 5 is fast enough for attaching many GPUs, so not include. Support for NVLink on - chip was previously unique selling point for POWER8 and POWER9.

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions.

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions

Thanks For The Memory

Ibm has revealed next generation of POWER processors. Upcoming POWER10 CPUs were designed to meet unique needs of enterprise hybrid cloud computing, focusing on its performance and energy efficiency across multitude of workloads. IBM POWER10 CPU Has Been Developed For Over 5 Years And IT Will Be Company's First Commercial 7nm CPU, Offering Up To 3x More Efficiency, Workload Capacity, And Container Density Than Its Predecessor. Featuring DDR5 and PCIe Gen5 support, this CPU will be available as single - chip and dual - chip modules, featuring up to 15 and 30 SMT4 / cores, respectively, with 2MB of L2 cache per core and up to 120MB of L3 cache. Co - developed Samsung, IBM POWER10 comes with multiple hardware enhancements to offer enhanced security for hybrid cloud environments. Some of these enhancements include hardware encryption for end - to - end security, faster cryptography performance, hardware - enforce container protection and isolation capabilities, and dynamic execution register control. With IBM POWER10, it is possible to create multi - Petabyte sized memory clusters thanks IBM Memory Inception technology. With this technology, clusters of POWER10 - base systems can and share each other's memory, reducing storage costs and POWER consumption. Ibm POWER10 is also prepared to deal with AI tasks thanks to embedded Math Accelerator. By offering up to 10x, 15x, and 20x faster AI inference for FP32, BFloat16 and INT8 computations, respectively, than CPU, IBM POWER10 is expected to help infuse AI workloads into typical enterprise applications. Ibm POWER10 Processor Is Expected To Be Available During Second Half Of 2021. Discuss on our page, HERE. Kitguru say: What would you do if you get your hands on one of these CPUs? Will IT able able to run Crysis?

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions.

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions

Sources

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions.

* Please keep in mind that all text is machine-generated, we do not bear any responsibility, and you should always get advice from professionals before taking any actions

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